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  tm may 20 FDMA1025P dual p-channel powertrench ? mosfet ?20 10 fairchild semiconductor corporation FDMA1025P rev.b 4 www.fairchildsemi.com 1 FDMA1025P dual p-channel powertrench ? mosfet  C20v, C3.1a, 155m: features ? max r ds(on) = 155m : at v gs = C 4.5v, i d = C 3.1a ? max r ds(on) = 220m : at v gs = C 2.5v, i d = C 2.3a ? low profile - 0.8mm maximum - in the new package microfet 2x2 mm ? rohs compliant general description this device is designed specifically as a single package solution for the battery charge switch in cellular handset and other ultra - portable applications. it features two independent p-channel mosfets with low on-state resistance for minimum conduction losses. when connected in the typical common source configuration, bi-directional current flow is possible. the microfet 2x2 package offers exceptional thermal per formance for its physical size and well suited to linear mode applications. application ? dc - dc conversion mosfet maximum ratings t a = 25c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage C 20 v v gs gate to source voltage 12 v i d drain current -continuous (note 1a) C 3.1 a -pulsed C 6 p d power dissipation for single operation (note 1a) 1.4 w power dissipation (note 1b) 0.7 t j , t stg operating and storage junction temperature range C 55 to +150 c r t ja thermal resistance single operation, junction to ambient (note 1a) 86 c/w r t ja thermal resistance single operation, junction to ambient (note 1b) 173 r t ja thermal resistance dual operation, junction to ambient (note 1c) 69 r t ja thermal resistance dual operation, junction to ambient (note 1d) 151 device marking device package reel size tape width quantity 025 FDMA1025P microfet 2x2 7 8mm 3000 units microfet 2x2 1 6 5 2 4 3 s1 g1 d2 d1 g2 s2 s2 g2 d1 d2 g1 s1 pin 1 d1 d2 1 3 2 6 5 4 ? free from halogenated compounds and antimony oxides
FDMA1025P dual p-channel powertrench ? mosfet FDMA1025P rev.b 4 www.fa irchildsemi.com 2 electrical characteristics t j = 25c unless otherwise noted symbol parameter test conditions min typ max units off characteristics bv dss drain to source breakdown voltage i d = C 250p a, v gs = 0v C 20 v ' bv dss ' t j breakdown voltage temperature coefficient i d = C 250p a, referenced to 25c 14 mv/ c i dss zero gate voltage drain current v ds = C 16v, C 1 p a v gs = 0v t j = 125c C 100 i gss gate to source leakage current v gs = 12v, v ds = 0v 100 na on characteristics v gs(th) gate to source threshold voltage v gs = v ds , i d = C 250p a C 0.4 C 0.9 C 1.5 v ' v gs(th) ' t j gate to source threshold voltage temperature coefficient i d = C 250p a, referenced to 25c C 3.8 mv/c r ds(on) drain to source on resistance v gs = C 4.5v, i d = C 3.1a 88 155 m : v gs = C 2.5v, i d = C 2.3a 144 220 v gs = C 4.5v, i d = C 3.1a,t j = 125c 121 220 g fs forward transconductance v ds = C 5v, i d = C 3.1a 6.2 s dynamic characteristics c iss input capacitance v ds = C 10v, v gs = 0v, f = 1mhz 340 450 pf c oss output capacitance 80 105 pf c rss reverse transfer capacitance 45 70 pf switching characteristics t d(on) turn-on delay time v dd = C 10v, i d = C 3.1a v gs = C 4.5v, r gen = 6: 510ns t r rise time 14 26 ns t d(off) turn-off delay time 13 24 ns t f fall time 816ns q g(tot) total gate charge at 4.5v v gs = 0v to C 4.5v v dd = C 10v i d = C 3.1a 3.4 4.8 nc q gs gate to source gate charge 0.8 nc q gd gate to drain miller charge 1.0 nc drain-source diode characteristics v sd source to drain diode forward voltage v gs = 0v, i s = C 1.1a (note 2) C 0.8 C 1.2 v t rr reverse recovery time i f = C 3.1a, di/dt = 100a/ p s 17 26 ns q rr reverse recovery charge 10 15 nc i s maximum continuous source-drain diode forward a C 1.1
FDMA1025P dual p-channel powertrench ? mosfet FDMA1025P rev.b 4 www.fa irchildsemi.com 4 notes: 1. r t ja is determined with the device mounted on a 1 in 2 oz. copper pad on a 1.5 x 1.5 in. board of fr-4 material. r t jc is guaranteed by design while r t ja is determined by the user's board design. (a) r t ja = 86 c/w when mounted on a 1 in 2 pad of 2 oz copper, 1.5 " x 1.5 " x 0.062 " thick pcb. for single operation. (b) r t ja = 173 c/w when mounted on a minimum pad of 2 oz copper. for single operation. (c) r t ja = 69 o c/w when mounted on a 1 in 2 pad of 2 oz copper, 1.5 x 1.5 x 0.062 thick pcb. for dual operation. (d) r t ja = 151 o c/w when mounted on a minimum pad of 2 oz copper. for dual operation. 2. pulse test : pulse width < 300 us, duty cycle < 2.0 a)86 o c/w when mounted on a 1 in 2 pad of 2 oz copper. b)173 o c/w when mounted on a minimum pad of 2 oz copper. c)69 o c/w when mounted on a 1 in 2 pad of 2 oz copper. d)151 o c/w when mounted on a minimum pad of 2 oz copper.
FDMA1025P dual p-channel powertrench ? mosfet FDMA1025P rev.b 4 www.fa irchildsemi.com 4 typical characteristics t j = 25c unless otherwise noted figure 1. 0123 0 1 2 3 4 5 6 -i d , drain current (a) -v ds , drain to source voltage (v) v gs = -3.5v pulse duration = 80 p s duty cycle = 0.5%max v gs = -2.5v v gs = -1.8v v gs =-4.5v on region characteristics figure 2. 0123456 0 1 2 3 4 5 v gs = -3.5v pulse duration = 80 p s duty cycle = 0.5%max normalized drain to source on-resistance -i d , drain current(a) v gs = -2.5v v gs = -1.8v v gs =-4.5v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i d =-3.1a v gs = -4.5v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 23456 0 100 200 300 400 500 pulse duration = 80 p s duty cycle = 0.5%max t j = 125 o c t j = 25 o c i d = -3.1a r ds(on) , drain to source on-resistance ( m : ) -v gs , gate to source voltage (v) o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 1.0 1.5 2.0 2.5 3.0 0 1 2 3 4 5 6 t j = -55 o c t j = 25 o c t j = 150 o c pulse duration = 80 p s duty cycle = 0.5%max -i d , drain current (a) -v gs , gate to source voltage (v) figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0001 0.001 0.01 0.1 1 10 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0v -i s , reverse drain current (a) -v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDMA1025P dual p-channel powertrench ? mosfet FDMA1025P rev.b 4 www.fa irchildsemi.com 5 figure 7. 02468 0 2 4 6 8 10 i d = -3.1a v dd = -12v v dd = -8v -v gs , gate to source voltage(v) q g , gate charge(nc) v dd = -10v gate charge characteristics figure 8. 0.1 1 10 10 100 1000 30 f = 1mhz v gs = 0v capacitance (pf) -v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage f i g u r e 9 . f o r w a r d b i a s s a f e op erating area 0.1 1 10 0.01 0.1 1 10 50 this area is limited by r ds(on) 100ms 10s 1s dc 10ms 1ms 100us single pulse t j = max rated r t ja =173 o c/w t a = 25 o c -i d , drain current (a) -v ds , drain to source voltage (v) 20 figure 10. 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 1 10 100 0.6 v gs = -4.5v single pulse p ( pk ) , peak transient power (w) t, pulse width (s) t a = 25 o c i = i 25 for temperatures above 25 o c derate peak current as follows: 150 t a C 125 ----------------------- - s i n g l e p u l s e m a x i m u m power dissipation figure 11. transient thermal response curve 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 0.001 0.01 0.1 1 duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (s) d = 0.5 0.2 0.1 0.05 0.02 0.01 single pulse p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a typical characteristics t j = 25c unless otherwise noted
FDMA1025P dual p-channel powertrench ? mosfet FDMA1025P rev.b 4 www.fairchild semi.com 6 dimensional outline and pad layout
FDMA1025P dual p-channel powertrench ? mosfet FDMA1025P rev. b 4 www.fairchildsemi.com 7 tr ade ma rks the f ollowi ng in clu des reg i ster ed an d un regist ered tr adema r ks a nd service ma rks, own ed by fair ch ild s emicondu ct or and/ or its gl obal su bsidiari es, a nd is no t int ende d t o be an exha ustive list o f all such tra demarks. * t rad e marks o f system ge nera l cor pora t io n, used un der license by fairchild s e micondu ct or. dis c laimer fairchild semicon duc to r r eserves the r i g h t to make ch anges with ou t fu rth e r n o ti c e to any pro d u c ts herein to impro v e r eliabi li ty, fun c ti on, or desi gn. fai r c h ild does not a ssu me any liabi li ty arising out of the applicati o n or use of an y pr odu c t or c i rc uit described herein; neither does it con vey an y license under it s pat en t ri ghts, nor t h e righ t s of others. these specif icati o ns do n o t expan d the t er m s of f airc h i l d? s worldwide terms and cond i t ion s, specif ically the war r anty therein, wh i c h c o ver s these pro ducts. li fe suppo r t po lic y fairchild?s products are not authorized fo r us e as critical compone n ts in l i fe support devices or sy stems without the exp ress wri t te n ap prov al of f a irchi ld s e mi conduct o r co r p orati o n. a s us ed he r e i n : 1. l i fe supp ort devices o r syste m s ar e devices o r syst ems whi c h , (a) a re in te nded f or surgical imp l ant i nto t he bod y or (b ) sup port or su st ain li fe, a nd (c) wh ose f a il ure to pe rf orm w h en prop erly used in acco rdan ce wit h in st ru ct ion s f o r use p rovided in t he lab e ling , can be reason ably e x p e cted t o result in a sig n if ica n t in jury of t he user. 2. a crit ical compo nent in any compon ent of a lif e sup port , device, or syst em wh ose f a il ure to p e rf orm ca n be reason ably ex pecte d to cause the f ailu re of t he l i fe supp ort de vi ce or syst em, or t o aff ect it s saf et y or eff e ct iveness. product s t a t us definitions defin i tion of term s a ccup o wer ? aut o-s pm? buil d i t now? corep l us? corep o wer? cr o ssv olt ? ct l ? curren t transf e r log ic? deuxpe ed ? dual cool? ec osp a rk ? e f f i cent max? esb c? fairchild ? fairchild s e micondu ct or ? fact quiet s e rie s ? fact ? fast ? fast vcore? fetbench? flashwrit e r ? * fps? f- pfs? fr f e t ? glob al power resour ce sm gree n f p s? gree n f p s? e- serie s ? g max ? gt o? intell imax? is opla nar? megab uck? microcoupler? mic r ofet? micr opak? micr opak2? millerdr i v e ? moti onmax? moti on-s p m? optihit? opt ol ogi c ? o p to pl a n ar ? ? pdp spm? power- spm? powertre nch ? powerx s? prog rammabl e a c t i ve droop ? qf et ? qs? quie t ser i es ? r a pidcon fig ure? saving ou r wo rld, 1 m w/w/ kw a t a time ? signa lwise? smart max? smart s t art? spm ? steal th? supe rfet? supe rsot?-3 supe rsot?-6 supe rsot?-8 supr emos? sy nc fe t? sync-lock? ? * the p o wer franchise ? ? tin y b oost? tiny buck ? tin y cal c ? t i ny lo g i c ? tinyo p to ? tin y power? tin y pwm? tin y wir e ? tri f a u lt detect? truecurrent? * se r d e s ? uhc ? ultra frfet? uni f e t ? vc x ? v isualmax? xs ? tm ? tm tm dat asheet identifi c a tion product s t a t us defini t i on a d va nc e in fo r m a tio n fo r m a t i ve / in de sig n dat ashe et cont ains the de si gn sp ecifi c a t io ns f or pro duct de ve lopmen t. s p ecificat ion s may cha nge in any manne r wi tho u t no tice. pre liminar y f irst p rodu c t ion dat a she e t cont ains preli m i nary dat a ; supple ment a ry da t a will be pub lished at a la te r dat e. fair ch ild semi co nduct or reserves th e r i ght t o make change s at any t i me wit hout not ice to impr ove d e sign. no ide nt i ficat i on nee ded full pr oduct i on dat a she e t cont ains fin a l sp ecificat ion s . f a ir child s emicondu ct or reser v e s t he righ t to make ch anges at a ny t i me with out n oti ce t o impro v e t he design . o b so le t e no t in p r od u c tio n dat a she e t cont ains sp ecificat ion s on a pro duct t hat i s discont inu ed by fai r ch ild semicon ducto r . t h e d at ashe et is fo r r efe rence inf orma tio n o nly . an ti-co unterfeiti n g po lic y fairchild s e micondu ct or cor porat ion ? s a n ti -count erf e it ing p o licy. fairchi l d?s ant i -coun te rfe i tin g policy is al so st at ed on our ext e rna l w e bsite , ww w. fairchi l dsemi. co m, und er sale s su pport . count erf e it ing o f semicond uctor p a rt s is a gro w i ng prob lem in t he indu st ry. a ll manuf act u res of semi co nduct or prod ucts are e x p e rien cin g co unt erf eit ing of th eir part s . custo m ers who ina dvert ent ly pur ch ase cou nte rfe i t par ts e x p eri en ce many prob lems such a s loss of b rand rep u t a ti on, subst a nda rd p erf orman c e , fa iled appl ica t io n, an d in cr eased cost of pr oduct i on and man ufa ct ur ing del a y s. fair ch ild is t a king stro ng measure s t o p rot ect oursel v e s and ou r cust omers fro m t he prol ife r at ion of co unt erf eit pa rts. fair ch ild st rong ly encou rage s cu st om er s to pur ch as e f a i r ch i l d p art s eit her dire ct ly f r om fa irchild or fro m author ized fai rchild dist rib ut ors who ar e liste d by count ry on o u r web p age cit ed a bove. prod ucts custo mers buy eit her fro m fairchild direct ly or f r om au th orized fai rchild dis t rib ut ors are gen uine part s , h a ve f u ll t ra c e abilit y, meet fairchil d?s qua lit y st and ards f o r h andi ng an d sto rage and provid e access to fairchild ?s fu ll ra nge o f up-t o -d at e t e chn i c a l and pro duct in for mat ion. fa irchild an d our aut h o rized distr ibut ors will s t an d behin d all warra nti e s a nd wi ll appr opria te ly ad dress and warran t y issues th at ma y ar ise. fair c h ild will n o t pr ovide an y war rant y c o v e rage o r ot her assista n ce fo r part s boug ht f rom una u th orized s ources. f a irchild i s co mmitt ed t o comb at t h is g l obal pr oblem and en co urag e o u r cu st omer s t o d o t hei r p a rt in sto ppin g t h is pract i ce b y buying di rect or f r om aut horized d i st rib uto rs. re v. i4 8 ?


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